A stable, regulated supply voltage (Vdd) is desirable in electronic circuits such as integrated circuits for processing systems, systems-on-chips (SoCs), etc. Abrupt changes in switching activity of the electronic circuits, for example, may cause a droop in supply voltage (referred to herein as, a “voltage droop”), inducing large current transients in voltage or power-delivery systems for the electronic circuits. Voltage droops can have a global effect across all circuits integrated on a semiconductor die and may be random and unpredictable in their occurrence.
Voltage droops can degrade the performance and energy efficiency of the electronic circuits, a problem which may be exacerbated in high-frequency or high performance designs. In an effort to mitigate the effects of voltage droops, some techniques identify a minimum acceptable operating voltage at which an electronic circuit can function at an acceptable frequency without degrading performance. A “guard band” is then calculated based on the worst case voltage droop which may be possible. The supply voltage is designed to be greater than the minimum acceptable operating voltage by at least the guard band. This way, even under the worst case voltage droop, the supply voltage would not fall below the minimum acceptable operating voltage. However, in designing for this worst case scenario (which, as noted above, may be random and possibly, relatively rare), the supply voltage is maintained at a much higher level even when there is no voltage droop, resulting in unnecessary wastage of power.
Other techniques to mitigate the effects of voltage droops involve adding hardware structures such as de-coupling capacitors to semiconductor dies or packages, but such structures are seen to be ineffective, especially in cases where the voltage droops may have large variation in their values.
Some conventional techniques also attempt to reduce the frequency of a system clock used to operate the electronic circuit, upon detection of a voltage droop in an effort to slow down the electronic circuit and maintain proper functionality at the lower supply voltage resulting from the voltage droop. For example, a feedback path may be provided to a phase-locked loop (PLL) used to generate the system clock, to indicate to the PLL that a voltage droop has occurred. Based on the indication, the PLL may reduce the frequency of the system clock (e.g., by a factor of two to reduce the operating frequency of the electronic circuit by half) to account for the reduced supply voltage. In some cases, a clock-divider circuit may be used to reduce the frequency of the clock generated by the PLL. In these approaches, a time lag or response time may be involved, from the point in time when the onset of the voltage droop is detected to the time when the clock frequency of the electronic circuit is reduced. This response time may be significant and span several clock cycles during which the electronic circuit may be operated at the original clock frequency but at the reduced supply voltage caused by the voltage droop. The voltage droops can have nearly immediate impact on the electronic circuit, particularly at high operating frequencies, and therefore the high response times in conventional techniques can expose the electronic circuit to various error conditions, some of which may be irreversible.
To combat the aforementioned problems associated with response times, an adaptive clock distribution (ACD) system has been proposed (see, e.g., U.S. patent application Ser. No. 14/668,041 filed on Mar. 25, 2015 and entitled “AUTOMATIC CALIBRATION CIRCUITS FOR IN-FIELD, OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS,” hereinafter, “the '041 Application”). In the event of a voltage droop, the ACD system of the '041 Application utilizes a clock-data delay compensation technique to provide an acceptable response time during which the clock frequency may be adaptively reduced without affecting the performance of the electronic circuit. In this regard, a tunable-length delay (TLD) element is provided in the ACD system, to introduce a TLD in a clock generation path of a system clock before the system clock is provided to a global clock distribution network. The TLD effectively prolongs the clock-data delay compensation in circuit paths of the electronic circuit for one or more clock cycles after the onset of a voltage droop, which provides a sufficient response time for adaptively reducing the clock frequency. The clock period at the output of the TLD element is designed to track the voltage variation in supply voltage for a time duration which is equal to the TLD. As the circuit paths slow down during the voltage droop, the clock period at the output of the TLD element increases to compensate for the slow down. Thus, the timing margin (calculated as clock period minus path delay) remains unchanged for a time duration which is equal to the delay of the TLD element. The ACD system also includes a dynamic variation monitor (DVM) or droop detector to detect the onset of the voltage droop, along with an adaptive control unit and clock divider to reduce clock frequency by half at the output of the TLD element to avoid timing-margin failures.
Although the above-described ACD system of the '041 Application can improve performance by adaptively responding to relatively rare voltage droops of large magnitudes, the performance benefits of the ACD system may reduce as the number of clock cycles at which the electronic circuit is operated at half the clock frequency Fclk increases. Accordingly, there is a continuing need in the art for effective techniques which can combat the negative effects of voltage droops in electronic circuits while avoiding the aforementioned limitations of prior approaches in this regard.